February 28, 2011
featured blogs
May 25, 2023
Register only once to get access to all Cadence on-demand webinars. Unstructured meshing can be automated for much of the mesh generation process, saving significant engineering time and cost. However, controlling numerical errors resulting from the discrete mesh requires ada...
May 24, 2023
Accelerate vision transformer models and convolutional neural networks for AI vision systems with the ARC NPX6 NPU IP, the best processor for edge AI devices.
The post Designing Smarter Edge AI Devices with the Award-Winning Synopsys ARC NPX6 NPU IP appeared first on New Hor...
May 8, 2023
If you are planning on traveling to Turkey in the not-so-distant future, then I have a favor to ask....
featured contest
 Join the AI Generated Open-Source Silicon Design ChallengeSponsored by Efabless Get your AI-generated design manufactured ($9,750 value)! Enter the E-fabless open-source silicon design challenge. Use generative AI to create Verilog from natural language prompts, then implement your design using the Efabless chipIgnite platform - including an SoC template (Caravel) providing rapid chip-level integration, and an open-source RTL-to-GDS digital design flow (OpenLane). The winner gets their design manufactured by eFabless. Hurry, though - deadline is June 2! |
featured chalk talk
dsPIC33CH DSCs: Two dsPIC33Cs on a Single Chip
Sponsored by Mouser Electronics and Microchip
In this episode of Chalk Talk, Vijay Bapu from Microchip and Amelia Dalton explore the benefits of dual core digital signal controllers. They discuss the key specifications to keep in mind when it comes to single core and dual core DSCs and how you can reduce your development time, save board space and cost and keep the performance and isolation you need with Microchip’s dsPIC33CH DSCs.