Synopsys 112G Ethernet PHY IP Solutions
Synopsys 112G Ethernet PHY IP solutions, an integral part of Synopsys' high-speed SerDes IP portfolio, enable true long, medium, very short and extra short (LR, MR, VSR, XSR) reach electrical channels, and CEI-112G-Linear, and CEI-112G-XSR+ optical interfaces. The silicon-proven IP enables up to 800G hyperscale data center, networking, AI, pluggable optical module and Ethernet switch SoCs requiring high bandwidth and low latency. Using leading-edge design, analysis, simulation, and measurement techniques, the Synopsys 112G Ethernet PHY IP solutions deliver exceptional signal integrity and jitter performance that exceeds the IEEE 802.3ck and OIF standards electrical specifications. The power-efficient PHYs are small in area and high in performance. The 112G Ethernet PHY for long and medium reach demonstrates excellent BER in greater than 45dB channels at less than 5pJ/bit. The 112G Ethernet PHY for very short reach demonstrates excellent BER in greater than 20dB channels at less than 3pJ/bit. The 112G XSR PHY IP demonstrates excellent BER in greater than 10dB channels at less than 1.4pJ/bit.
The PHYs’ flexible layout maximizes bandwidth per die-edge by allowing the placement of square macros in a multi-row structure and along all edges of the die. Support for the Pulse-Amplitude Modulation 4-Level (PAM-4), Non- Return-to-Zero (NRZ) signaling, and independent, per-lane data rates allows ultimate flexibility to address a broad range of protocols and applications.Combined with Synopsys' routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis, Synopsys provides a comprehensive 112G Ethernet PHY IP products for fast and reliable SoC integration. Additional ResourcesSemiWiki article:Very Short Reach (VSR) Connectivity for Optical Modules
Webinar:Keeping Latency to a Minimum with 400G/800G Ethernet IP
Article:Anatomy of an Integrated Ethernet PHY IP for High Performance Computing SoCs
Article:Tightly-Coupled Analog and DSP Architecture for Best 112G SerDes IP Performance
News:Synopsys Demonstrates Silicon Proof of Synopsys 112G Ethernet PHY IP in 5nm Process for High-Performance Computing SoCs
Web page:Synopsys High-Speed SerDes PHY IP solutions
Synopsys 112G Ethernet PHY IP DatasheetSynopsys USR/XSR PHY IPSynopsys 112G Ethernet PHY IP for Very Short Reach
|
|
- Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
- Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
- Supports IEEE 802.3ck and OIF standards electrical specifications
- Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
- Provides comprehensive 200G/400G/800G solution with routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis
- LR, MR and VSR: DAC-based PAM-4 transmitter includes feed forward equalization (FFE)
- LR, MR and VSR: Digital-based receiver consists of analog front-end (AFE), ADC, and digital signal processor (DSP)
- High-performance receive equalization supporting required channel loss
- Continuous calibration and adaptation (CCA) algorithms provide robust performance across process, voltage, and temperature variations
- Low jitter phase-locked loops (PLLs) provide robust timing recovery and better jitter performance